Halo region formation by epitaxial growth

ABSTRACT

A structure including a semiconductor substrate including a source region and a drain region, a gate located above the semiconductor substrate and between the source region and the drain region, and two opposing halo regions being part of the source and drain regions, respectively, the halo regions being grown epitaxially, wherein the source region and the drain region include a stressor material.

BACKGROUND

The present invention relates to semiconductor devices including a dopedsubstrate and a method for manufacturing the same, and moreparticularly, the present invention relates to semiconductor devicesincluding field effect transistors and halo doped regions, and a methodfor making the same.

In semiconductor manufacturing, complementary metal-oxide-semiconductor(CMOS) technology is commonly used for fabricating field effecttransistors (FETs) as part of advanced integrated circuits, such asCPUs, memory, storage devices, and the like. In FETs, a channel regionmay be formed in an n-doped or p-doped semiconductor substrate on whicha gate structure is created. The overall fabrication process may includeforming a gate structure over a channel region. The channel region mayconnect a source region and a drain region within the substrate. Thesource and drain regions may be on opposite sides of the gate, typicallywith some vertical overlap between the gate and the source and drainregions.

A desired characteristic in CMOS manufacturing is the presence of a haloregion. A halo region may be generally located interposed between thesource and drain regions and the channel region, and may be of conversepolarity to the source and drain regions. The presence of a halo regionmay reduce drain-source current leakage (punch-through effect) withinthe FET.

Halo regions may typically be formed through a low energy, low currention implantation method carried out at large angle tilt after a gate andgate dielectric are in place. The gate and gate dielectric act as an ionimplantation mask allowing implanted dopants to penetrate below the edgeof the metal-oxide semiconductor gate stack. This particular method mayhinder halo region implantation in faceted recess structures.Furthermore, the low energy, low current ion implantation methoddescribed above may compromise performance of FET devices already on thestructure, since halo ion implantation may provide undesirable haloresidual atoms physically at or near the FET gate dielectric. Inaddition, as the industry continues to move towards smaller scaledevices, halo region implantation becomes even harder due to spacereduction between gates (gate shadowing), which may also increase theundesirable effects described above. Additionally, when significantsubstrate removal occurs during the fabrication of faceted recessstructures on a semiconductor substrate, integrity of the implanted haloregion may be compromised given that the highest halo concentration islocated where the faceted recess is produced.

Therefore, it would be desirable to provide a method and a structurehaving a field effect transistor on a substrate, and the substrateincluding a well-defined halo region wherein the halo region formationdoes not require ion implantation.

SUMMARY

According to at least one exemplary embodiment of the presentdisclosure, a method of forming a semiconductor device includes: forminga gate on a semiconductor substrate, forming a gate dielectric betweenthe gate and the substrate, forming a source recess and a drain recessin the semiconductor substrate on opposing sides of the gate,epitaxially growing an embedded halo region along a perimeter of each ofthe source and drain recesses, etching a bottom area along the perimeterof both the source and drain, and epitaxially growing a stressormaterial to fill the source and drain recesses, wherein the filledsource and drain recesses form source and drain regions for conductingcurrent through the channel.

According to another exemplary embodiment of the present disclosure, asemiconductor device comprises: a semiconductor substrate definingmultiple recesses in the substrate, a gate located above a semiconductorsubstrate between the source and drain recesses, a gate dielectricbetween the semiconductor substrate and the gate, a source recess and adrain recess in the semiconductor substrate on opposing sides of thegate, an epitaxially grown halo region partially along a perimeter ofeach of the source and drain recesses, an epitaxially grown stressormaterial inside the source and drain recesses and communicating with atop and bottom region of the recesses, such that the recesses define asource region and a drain region in the semiconductor substrate, and achannel region positioned between the source and drain recesses.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The features and advantages of the present disclosure will becomeapparent from the following detailed description of illustrativeembodiments thereof, which is to be read in connection with theaccompanying drawings. The various features of the drawings are not toscale as the illustrations are for clarity in facilitating one skilledin the art in understanding the disclosure in conjunction with thedetailed description. The detailed description should be consulted foraccurate dimensions. The drawings are intended to depict only typicalembodiments of the invention, and therefore should not be considered aslimiting the scope of the invention. In the drawings, like numberingrepresents like elements. In the drawings:

FIG. 1 is a cross sectional side elevational view of a gate layer andsigma-shaped source and drain recesses formed onto a semiconductorsubstrate, according to one embodiment of the present disclosure;

FIG. 2 is a cross sectional side elevational view of an epitaxial haloregion formed on a perimeter of the sigma-shaped source and drainrecesses shown in FIG. 1, according to one embodiment of the presentdisclosure;

FIG. 3 is a cross sectional side elevational view depicting a bottompart of the sigma-shaped source and drain recesses being etched toremove part of the halo region shown in FIG. 2, according to oneembodiment of the present disclosure;

FIG. 4 is a cross sectional side elevational view depicting an epitaxialembedded stressor material region formed between the halo regions tofill the sigma-shaped source and drain recesses shown in FIG. 3,according to one embodiment of the present disclosure;

FIG. 5 is a cross sectional side elevational view depicting an initialstep in the formation of an optional first epitaxial halo region locatedbelow the channel region in each of the source and drain recesses,according to one embodiment of the present disclosure;

FIG. 6 is a cross sectional side elevational view depicting theformation of sigma-shaped source and drain recesses including anoptional first epitaxial halo region below the channel region, accordingto one embodiment of the present disclosure;

FIG. 7 is a cross sectional side elevational view depicting a secondepitaxial halo region formed adjacent to the optional first epitaxialhalo region. The second epitaxial halo region located in a top portionof the perimeter of the sigma-shaped source and drain recesses,according to one embodiment of the present disclosure;

FIG. 8 is a cross sectional side elevational view depicting a bottompart of the sigma-shaped source and drain recesses being etched toremove part of the second halo region shown in FIG. 7, according to oneembodiment of the present disclosure;

FIG. 9 is a cross sectional side elevational view depicting an epitaxialstressor material region formed in the sigma-shaped source and drainrecesses shown in FIG. 8, according to one embodiment of the presentdisclosure; and

FIG. 10 is a flow chart showing a method for the fabrication of sourceand drain regions containing an epitaxial halo within a semiconductorsubstrate, according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein withreference to the accompanying drawings, in which exemplary embodimentsare shown. This disclosure may, however, be embodied in many differentforms and should not be construed as limited to the exemplaryembodiments set forth herein. Rather, these exemplary embodiments areprovided so that this disclosure will be thorough and complete and willfully convey the scope of this disclosure to those skilled in the art.In the description, details of well-known features and techniques may beomitted to avoid unnecessarily obscuring the presented embodiments.

Referring to FIGS. 1-10, according to an illustrative embodiment of thepresent disclosure, a method for manufacturing a semiconductor structureis shown. Specifically, FIGS. 1-10 depict a semiconductor processingtechnique for providing a semiconductor structure 400 shown in FIG. 4and an alternate structure 900 shown in FIG. 9.

Referring now to FIG. 1, according to an embodiment of the presentdisclosure, an initial structure 100 may include a semiconductorsubstrate embodied as a silicon substrate 102. The semiconductorsubstrate may be made of any semiconductor material including, but notlimited to: silicon, germanium, silicon-germanium alloy, carbon-dopedsilicon, carbon-doped silicon-germanium alloy, and compoundsemiconductor materials. FIG. 1 illustrates the formation of a gatestructure 104 above a channel region 114 of the semiconductor substrate102. The gate 104 may include a gate dielectric 108 which may be formedby any method known in the art. The gate dielectric 108 may include ahigh-k dielectric material having a dielectric constant greater than,for example, 3.9, which is the dielectric constant of silicon oxide. Insome embodiments, multiple gates may be formed above the channel region114 when fabricating multiple transistor structures having shared sourceand drains. The semiconductor structure 100 may further include a gatespacer 106. The gate spacer 106 may be formed on the sidewalls of thegate 104 by deposition of a dielectric layer. The dielectric layer maybe formed by any known technique in the art, for example, by chemicalvapor deposition (CVD) of a dielectric material. In another embodimentof the present invention, the gate 104 may be formed in a gate lastprocess where the initial gate structure may comprise a dummypolysilicon gate that may be replaced by a final metal gate structure104 after device manufacturing is complete.

In the present embodiment, source and drain recesses 110 may be formedadjacent to a channel region 114 in a substrate 102. The recesses may beformed by etching the semiconductor substrate 102 using a dry etchingtechnique. Initial recesses in the semiconductor substrate 102 may havea box shape (not shown), which are then processed to the present sigmashape. Sigma-shaped source and drain recesses 110 as shown in theinitial structure 100 may be made utilizing conventional techniques wellknown to those skilled in the art. For example, anisotropic dry-etchingfollowed by anisotropic wet-etching. The sigma-shaped source and drainrecesses 110 may also be referred to as diamond-shaped recesses.Sigma-shaped recesses 110 may be formed to increase strain force on thechannel region 114 by narrowing the space between source and drain.

Referring now to FIG. 2, structure 200 illustrates epitaxial growth of adoped material layer in the device source and drain recesses. The sourceand drain recesses 110 may include a perimeter 112, as shown in FIG. 1,defining the recesses in the substrate 102. The epitaxial growth may beconducted along the perimeter 112 of each of the source and drainrecesses 110 shown in FIG. 1. The epitaxial growth of the doped materiallayer may form a halo region 202 at each of the source and drainrecesses 110, of inverse doping characteristics to the source and drainregions (discussed below), respectively.

The thickness of the epitaxial halo region 202 may vary according to thedevice structure and the desired device characteristics, includingdoping of the halo region 202. For example, the thickness of theepitaxial halo region 202 may be in the range of about 2-10 nm. Theepitaxial halo region 202 may be formed from a crystalline structurewhich has the same lattice constant as the underlying semiconductorsubstrate 102. Dopants may be incorporated into the epitaxial haloregion 202 by in-situ doping. For example, for a p-FET structure ann-type halo dopant such as phosphorus or arsenic may be utilized. Aphosphorus or arsenic doped silicon (Si:P or Si:As) material orphosphorus or arsenic doped silicon-germanium (SiGe:P or SiGe:As)material may be grown, where the concentration of phosphorus or arsenicmay range from 5×10¹⁷ cm⁻³ to 1×10¹⁹ cm ⁻³. Similarly, for an n-FETstructure a p-type dopant such as boron may be incorporated by in-situdoping in the epitaxial halo region. The concentration of boron mayrange from 5×10¹⁷ cm⁻³ to 1×10¹⁹ cm⁻³.

The halo regions 202 provide improved channel region 114 isolationwithin the FET device 200. Halo regions are areas of opposite higherdopant concentration in close proximity to the device gate. Usually haloregions are located underneath the device gate 104 and the inversionchannel 114. Halo regions are commonly used to avoid punch-througheffect in short-channel devices.

A tilted ion implantation method is typically used to introduce therequired dopant species into the substrate 102. Because of thecontinuous reduction of transistor dimensions, high-angle ionimplantation method may result in undesirable residual halo implantationions at or near the gate hence compromising FET performance. Incontrast, in-situ doped halo regions formed by a selective epitaxialgrowth process may provide well-defined halo regions with the desireddopant profile without affecting FET performance especially for 22nmtechnologies and beyond.

Referring to FIG. 3, a bottom portion of the halo region 202 shown inFIG. 2 may be removed, for example, by a directional reactive-ionetching technique (RIE). The removal of this portion of the halo regionmay be performed to provide a butting contact area 304 within the device300. The technique then includes filling the sigma-shaped recesses 110with a stressor material, such as embedded silicon germanium (eSiGe) forp-FET devices or carbon-doped silicon (Si:C) for n-FET devices. Thestressor material may apply a stress onto the channel region 114, thusimproving device performance.

Referring to FIG. 4, according to one embodiment of the presentdisclosure, a stressor material 402 may be grown epitaxially within thesource and drain recesses 110 shown in FIG. 3 to form the source anddrain regions 404 of the semiconductor device 400. The stressor materialusually has a larger lattice constant for p-FET devices or a smallerlattice constant for n-FET devices than that of the semiconductorsubstrate 102 in order to apply a compressive or a tensile strain intothe channel region 114 respectively. Lattice stress may be transferredfrom the source and drain regions 404 to the underlying semiconductorsubstrate 102.

Source and drain regions 404 include the stressor material 402 and thehalo regions 302. The halo regions 302 can be considered adjacent to thestressor material 402 and part of the source and drain regions 404.

For example, for a p-FET device, the epitaxially grown stressor materialmay include a silicon-germanium (SiGe) material, where the atomicconcentration of germanium (Ge) may range from about 10-80%. In anembodiment of the present disclosure, the concentration of germanium(Ge) may be 25-50%. The epitaxially grown stressor material may providea compressive strain to the channel region 114. More specifically, thestressor material region may induce a compressive stress in the p-FETchannel region 114 which enhances carrier mobility and increases drivecurrent. Thus, the source and drain regions 404 may include enhancedcarrier mobility provided by the epitaxial stressor material andeffective current isolation provided by the epitaxial halo region 302.Dopants such as boron may be incorporated into the silicon-germaniumepitaxial region by in-situ doping. The percentage of boron may rangefrom 1×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³, preferably 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.

For example, for an n-FET device, the epitaxially grown stressormaterial may include a carbon-doped silicon (Si:C) material, where theatomic concentration of carbon (C) may range from about 0.4-3.0%. Theepitaxially grown stressor material may provide a tensile strain to thechannel region 114. More specifically, the stressor material region mayinduce a tensile stress in the n-FET channel region 114 which enhancescarrier mobility and increases drive current. Thus, the source and drainregions 404 may include enhanced carrier mobility provided by theepitaxial stressor material region and effective current isolationprovided by the epitaxial halo region 302. Dopants such as phosphorus orarsenic may be incorporated into the carbon-doped epitaxial region byin-situ doping. The percentage of phosphorus or arsenic may range from1×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³, preferably 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.

Referring to FIG. 5, in another embodiment of the present invention, aninitial structure 500 depicts the formation of a doped material layerregion in the lower part of preliminary box-shaped source and drainrecesses 103. The process may include epitaxially growing a dopedsacrificial layer 504 in the box-shaped source and drain recesses 502.The sacrificial layer 504 may comprise the epitaxial growth ofsilicon-germanium (SiGe) or carbon-doped silicon (Si:C) with thecorresponding dopants, according to p-FET or n-FET structures. Followingthe formation of the sacrificial layer 504, an in-situ etching processmay be conducted to form sigma-shaped source and drain recesses.

Referring now to FIG. 6, sigma-shaped recesses 110 may be formed byetching the semiconductor substrate 102 using any suitable etchingtechnique, for example the substrate 102 may be etched using an in-situgas-phase hydrochloric acid (HCl) etching procedure. A bottom haloregion embodied as an optional first halo region 602 may be epitaxiallygrown in the recesses before forming the sigma-shaped recesses 110, asdescribed in FIG. 5. This optional doped region 602 may form a firsthalo region located below the channel region 114 that can be extendedforming a second halo region 202 (as shown in FIG. 2) following theprocedure previously described in FIGS. 1-4. In short channel devices,there is a possibility for space charge regions (SCR), associated withsource and drain regions, to come into close contact with each otherwhich in turn increases punch-through effect. The presence of a haloregion near the source and drain regions and beneath the inversionchannel suppresses the width of the space charge regions, hence reducingpunch-through effect.

The thickness of the epitaxially grown first halo region 602 may varyaccording to the device structure and the device desired characteristicsincluding doping of the first halo region 602. For example, thethickness of the first epitaxial halo region 602 may be in the range ofabout 2-10 nm. Dopants may be incorporated into the optional halo region602 by in-situ doping. For example, for a p-FET structure an n-type halodopant such as phosphorus or arsenic may be utilized. A phosphorus orarsenic doped silicon (Si:P or Si:As) material or phosphorus or arsenicdoped silicon-germanium (SiGe:P or SiGe:As) material may be grown, wherethe concentration of phosphorus or arsenic may range from 5×10¹⁷ cm⁻³ to1×10¹⁹ cm⁻³. Similarly, for an n-FET structure a p-type dopant such asboron may be incorporated by in-situ doping in the epitaxial haloregion. The concentration of boron may range from 5×10¹⁷ cm⁻³ to 1×10¹⁹cm ⁻³.

Referring now to FIG. 7, subsequent to the formation of the firstepitaxial halo region 602, a second doped region 202 may be epitaxiallygrown on a perimeter 112 of the source and drain recesses 110. Theformation of a second epitaxial halo region 202 follows the techniqueregarding in FIG. 2. Dopants may be incorporated into the secondepitaxial halo region 202 by in-situ doping. For example, for a p-FETstructure an n-type halo dopant such as phosphorus or arsenic may beutilized. A phosphorus or arsenic doped silicon (Si:P or Si:As) materialor phosphorus or arsenic doped silicon-germanium (SiGe:P or SiGe:As)material may be grown, where the concentration of phosphorus or arsenicmay range from 5×10¹⁷ cm⁻³ to 1×10¹⁹ cm ⁻³. Similarly, for an n-FETstructure a p-type dopant such as boron may be incorporated by in-situdoping in the epitaxial halo region. The concentration of boron mayrange from 5×10¹⁷ cm⁻³ to 1×10¹⁹ cm ⁻³.

Referring to FIG. 8, the bottom part of the second halo region 202 shownin FIG. 7 may be removed, for example, by a directional reactive-ionetching technique (RIE). The removal of this portion of the second haloregion may be performed to provide a butting contact area 802 within thedevice 800. The technique then may include filling the sigma-shapedrecesses 110 with a stressor material, such as embedded silicongermanium (eSiGe) for p-FET devices and carbon-doped silicon (Si:C) forn-FET devices. The stressor material may apply a stress onto the channelregion 114, thus improving device performance.

The first epitaxial halo region 602 and the second epitaxial halo region302 may form an extended halo region 804 along the perimeter 112 of thesource and drain recesses 110. The extended halo region 804 may furtherimprove carrier mobility within the FET device.

Referring now to FIG. 9, a stressor material region 902 may be formed tofill the source and drain recesses 110 shown in FIG. 8, in order toincrease the strain force applied to the channel region 114. Thestressor material region 902 may be similar to, and formed similarly to,the stressor material region 402 of FIG. 4. The epitaxial stressormaterial region 902 and the extended epitaxial halo region 804 may formthe device source and drain regions 904.

For example, for a p-FET device, an epitaxially grown stressor material902 may include a silicon-germanium (SiGe) material, where the atomicconcentration of germanium (Ge) may range from about 10-80%. In anembodiment of the present disclosure, the concentration of germanium(Ge) may be 25-50%. The epitaxially grown stressor material 902 embodiedas an embedded silicon-germanium region in structure 900, may provide acompressive strain to the channel region 114. More specifically, thestressor material region 902 may induce a compressive stress in thep-FET channel region 114 which enhances carrier mobility and increasesdrive current. Thus, the source and drain regions 904 may includeenhanced carrier mobility provided by the epitaxial stressor materialregion 902 and effective current isolation provided by the extendedepitaxial halo region 804. Dopants such as boron may be incorporatedinto the silicon-germanium epitaxial region by in-situ doping. Thepercentage of boron may range from 1×10¹⁹ cm⁻³ to 2×10²¹ cm ⁻³,preferably 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.

For example, for an n-FET device, an epitaxially grown stressor material902 may include a carbon-doped silicon (Si:C) material, where the atomicconcentration of carbon (C) may range from about 0.4-3.0%. Theepitaxially grown stressor material 902 embodied as an embeddedcarbon-doped silicon region in structure 900, may provide a tensilestrain to the channel region 114. More specifically, the stressormaterial region 902 may induce a tensile stress in the n-FET channelregion 114 which enhances carrier mobility and increases drive current.Thus, the source and drain regions 904 may include enhanced carriermobility provided by the epitaxial stressor material region 902 andeffective current isolation provided by the extended epitaxial haloregion 804. Dopants such as phosphorus or arsenic may be incorporatedinto the carbon-doped epitaxial region by in-situ doping. The percentageof phosphorus or arsenic may range from 1×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³,preferably 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.

Referring now to FIG. 10, a flowchart depicting the formation of sourceand drain regions within a semiconductor substrate is shown. The mainprocess consists of several consecutive steps (1010, 1012, 1014, 1018,1020 and 1022) to achieve sigma-shaped source and drain with awell-defined halo region. The method described in FIG. 10 includes anoptional process 1016 that may comprise the formation of a first haloregion in the bottom part of the source and drain recesses below thedevice channel region. Such optional halo region may be epitaxiallygrown before etching the semiconductor substrate to form sigma-shapedrecesses. Once the optional first halo region 1016 is formed, a secondhalo region may be grown following steps 1018 and 1020. Subsequently, anepitaxial stressor material 1022 may be grown within the source anddrain recesses to ultimately obtained sigma-shaped source and drain witha well-defined extended halo region.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableother of ordinary skill in the art to understand the embodimentsdisclosed herein. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustratedbut fall within the scope of the appended claims.

We claim:
 1. A semiconductor device, comprising: a semiconductorsubstrate comprising a source region and a drain region; a gate locatedabove the semiconductor substrate and between the source region and thedrain region; and two opposing halo regions being part of the source anddrain regions, respectively, the halo regions being grown epitaxially,wherein the source region and the drain region include a stressormaterial.
 2. The structure of claim 1, wherein the two opposing haloregions, each having a triangular shape, form a sigma-shaped sourceregion and a sigma shaped-drain region.
 3. The structure of claim 1,wherein the embedded halo region has a crystalline orientation which isthe same as a crystalline orientation in the semiconductor substrate. 4.The structure of claim 1, wherein the stressor material in each of thesource and drain regions comprise opposite doping polarity to theirrespective halo regions.
 5. The structure of claim 1, furthercomprising: a bottom halo region located beneath each of the source anddrain regions and communicating within the source and drain regions, thebottom halo region being positioned below the channel region.
 6. Thestructure of claim 5, wherein the bottom halo region comprises growingan epitaxial halo with in-situ dopants.